1. Field of the Invention
The present invention generally relates to testing technology for semiconductor integrated circuit devices, and more particularly, to a burn-in test system which can select IC devices at any location on a test board depending on the test patterns or the choice of the operator.
2. Description of the Related Art
Most semiconductor IC device failures occur within the first one thousand hours after they are produced. If failures or defects are not found during that initial time period, the IC devices are believed to be reliable and are delivered to customers for installation in a system. In order to screen out the defective devices that have a short life span, IC device manufacturers perform a burn-in test which environmentally (thermally and/or electrically) stresses the IC devices to accelerate any failures or defects resident in the device.
The burn-in tests are performed on packaged IC devices, and can be divided into three types; a static burn-in test, a dynamic burn-in test, and a monitor burn-in test.
During static burn-in tests, only power supply signals are supplied to the devices while thermal stress is being applied. The static burn-in test is mainly used to test linear devices and logic devices.
The dynamic burn-in test is performed by providing a power source, several electrical signals, and data for the devices so that electrical stress as well as thermal stress can be applied to the devices to simulate real-life operation conditions. The dynamic burn-in test is generally suitable for testing memory devices.
In the monitor burn-in test, the acceleration of early failures is achieved by thermally and electrically stressing the devices, accompanied by a functional test that measures output signals from the devices. Once the devices are loaded into a test system or test board, they can be exercised or tested under a variety of stresses, whereby their proper function and operation can be verified without removing them from the burn-in test board. Therefore, it is possible to reduce the total test time and to optimize the test time. Presently, the monitor burn-in is mainly used to test memory devices, and thus is usually called "Memory Burn-In".
The monitor burn-in test uses test boards where many (e.g., 128) IC devices to be tested are mounted. The test board is then inserted into an oven or a chamber which comprises a temperature controller for subjecting the devices to an increased temperature condition for accelerating their early failure. For electrically stressing the devices, terminals of the devices are connected in parallel to signal supply pins of a test system, where increased voltage and high current are supplied to the devices. The thermal and electrical stress applications can be performed at one time on all the devices mounted on the test board, even when the number of the input/output pins of the test system is limited. However, when performing the functional test portion of the monitor burn-in, the different input/output pins of the test system must be connected to the output terminals of the devices. Accordingly, the monitor burn-in system uses scanning signals for selecting particular devices mounted on the test board, but in the conventional system only one or two devices are selected at the same time by the scanning signals.
The specific number of devices selected by the scanning signals varies, and is determined with reference to the number of data bits of the output signals from the device and total data input pins of the test system. For example, if the number of data input pins is `m` and the output signals have `a` bits, the maximum number of the selected devices would be `b`, with the relationship m=a.times.b or b=m/a. If only a small number of devices are selected at one time for functional testing, the testing process time increases and the efficiency of the monitor burn-in test decreases.
The device selection problem is particularly pertinent when devices that operate in both merged data output mode and normal standard mode are tested using a single test board as described in U.S. Pat. application Ser. No. 08/967,016, filed Nov. 10, 1997, entitled "TEST BOARD FOR TESTING IC DEVICES OPERATING IN MERGED DATA OUTPUT MODE OR STANDARD MODE" (Attorney Docket No. SEC.351), which is hereby incorporated by reference its entirety.
A need exists, therefore, for a test system where the selection pattern for the devices is not fixed, but rather is flexible or adjustable to various test patterns so that devices at any location on the test board can be selected depending on the test patterns and/or the operator's choice.